The present invention is directed, in general, to methods of manufacturing semiconductor devices and, more specifically, to a method of manufacturing a bipolar transistor having an oxygen implanted emitter window.
The advent of the integrated circuit has had a significant impact on various types of communication devices. The integrated circuit has been incorporated into both radio frequency applications and high speed communication network systems. While operation speeds of these communication devices have dramatically increased, the demand for yet faster communication devices continues to rise. Thus, the semiconductor manufacturing industry continually strives to increase the overall speed of the integrated circuit. One way in which the semiconductor industry has increased the speed of the integrated circuit is to continue to shrink the size of the transistor. Over the last few years, the device size of the transistor has gone from 0.5 xcexcm to 0.32 xcexcm to 0.25 xcexcm and now transistor device sizes are heading to the 0.12 xcexcm range and below. With each decrease in size, the semiconductor industry has faced new challenges.
One such challenge is controlling the thickness of the interfacial oxide region between the emitter and the base or collector. Variations in the thickness of the oxide region between the emitter and the base may result in wafer to wafer or lot to lot variations in device current gain and breakdown voltage. Additionally, in load-lock furnaces, especially those employed in exceptionally clean fabrication environments, the difficulty in controlling the thickness of the oxide region may result in entirely eliminating current gain. For example, the interfacial oxide region developed in load-lock furnaces utilized in exceptionally clean fabrication environments may grow to thicknesses varying from wafer to wafer and from lot to lot anywhere between 0-1 nm, resulting in undesirable gain and breakdown voltage variation from wafer lot to wafer lot.
Previous attempts to resolve the lack of uniformity of the oxide region thickness have included employing ozonated, deionized water proximate the emitter area to form an interfacial oxide region prior to depositing the poly silicon. While this provides slight improvement in current gain as well as moderate uniformity from wafer to wafer and lot to lot, it does not completely resolve the current gain and uniformity issues as desired. Additionally, such an approach does not provide precise control over the thickness of the resulting oxide region.
Accordingly, what is needed in the art is a method of manufacturing a bipolar transistor that avoids the disadvantages associated with the prior art bipolar transistor manufacturing methods.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing a bipolar transistor. In one embodiment, the method comprises forming a collector in a semiconductor wafer substrate, forming a base in the collector, and implanting an oxide region within the collector and over the base. The method further comprises forming an emitter over the substrate such that the oxide region is located between the emitter and the base.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the pertinent art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the pertinent art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the pertinent art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.